1. Field of the Invention
The present invention relates to methods for forming semiconductor structures and systems for forming semiconductor structures, and more particularly to methods for forming gate structures and systems for forming gate structures.
2. Description of the Related Art
With advances associated with electronic products, semiconductor technology has been widely applied in manufacturing memories, central processing units (CPUs), liquid crystal displays (LCDs), light emission diodes (LEDs), laser diodes and other devices or chip sets. In order to achieve high integration and speed targets, dimensions of semiconductor integrated circuits, such as width of gate structures, continue shrinking.
FIGS. 1A and 1B are schematic cross sectional views showing undercuts of a gate structure and footings of a gate structure.
Referring to FIG. 1A, shallow trench isolation structures 105 are formed within a substrate 100. A gate dielectric layer 110 and a polysilicon layer 120 are sequentially formed over the substrate 100. The stacked structure of the gate dielectric layer 110 and the polysilicon layer 120 is generally referred to as a gate structure. The gate structure can be formed by forming a dielectric layer and a layer of polysilcion material over the substrate 100. The dielectric layer and the layer of polysilicon material are then subjected to a photolithographic process and an etch process, thereby forming the gate dielectric layer 110 and the polysilicon layer 120. As shown in FIG. 1A, undercuts 115 undesirably exist at the bottom of the region of the gate structure, i.e., the bottom of the polysilicon layer 120 and the gate dielectric layer 110. Under some etch conditions, a gate structure including a gate dielectric layer 130 and a polysilicon layer 140 are formed over the substrate 100 and include footings 135 as shown in FIG. 1B. The footings 135 of the gate structure are undesirably formed at the bottom region thereof.
As described above, dimensions, e.g., width, of gate structures continue to shrink. Minor variations in the width of gate structures may significantly affect electrical characteristics of transistors formed from the gate structures. For example, the undercuts 115 shown in FIG. 1A increase resistance of the gate structure due to the small cross sectional area of the polysilicon layer 120. Further, the smaller width “w1” at the bottom of the polysilicon layer 120 may also result in short channel effects, thereby adversely affecting currents and threshold voltages of the transistor using the gate structure. The footings 135 of FIG. 1B also present problems as they reduce resistance of the gate structure due to its large cross sectional area. In addition, the large width “w2” of the polysilicon layer 130 may also undesirably affect transistor threshold voltages and operating currents. It would therefore be desirable to eliminate the aforementioned shortcomings associated with the footings and undercuts.
Based upon the foregoing, it can be seen that improved methods and systems for forming gate structures are desired.